852 search results - page 31 / 171 » Categories, Allegories and Circuit Design |
DAC
2007
ACM
16 years 24 days ago
2007
ACM
In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case condit...
GLVLSI
2009
IEEE
15 years 6 months ago
2009
IEEE
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
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FPGA
2008
ACM
15 years 1 months ago
2008
ACM
Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
DAC
2006
ACM
16 years 23 days ago
2006
ACM
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
DAC
2005
ACM
16 years 23 days ago
2005
ACM
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...