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ICCAD
2006
IEEE
165views Hardware» more  ICCAD 2006»
15 years 8 months ago
A fast block structure preserving model order reduction for inverse inductance circuits
Most existing RCL−1 circuit reductions stamp inverse inductance L−1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describ...
Hao Yu, Yiyu Shi, Lei He, David Smart
CF
2004
ACM
15 years 5 months ago
Opportunities and challenges in application-tuned circuits and architectures based on nanodevices
Nanoelectronics research has primarily focused on devices. By contrast, not much has been published on innovations at higher layers: we know little about how to construct circuits...
Teng Wang, Zhenghua Qi, Csaba Andras Moritz
SLIP
2009
ACM
15 years 6 months ago
A pre-placement net length estimation technique for mixed-size circuits
An accurate model for pre-placement wire length estimation can be a useful tool during the physical design of integrated circuits. In this paper, an a priori wire length estimatio...
Bahareh Fathi, Laleh Behjat, Logan M. Rakai
GLVLSI
2006
IEEE
193views VLSI» more  GLVLSI 2006»
15 years 5 months ago
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ISLPED
2004
ACM
169views Hardware» more  ISLPED 2004»
15 years 5 months ago
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
Deming Chen, Jason Cong