Most existing RCL−1 circuit reductions stamp inverse inductance L−1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describ...
Nanoelectronics research has primarily focused on devices. By contrast, not much has been published on innovations at higher layers: we know little about how to construct circuits...
An accurate model for pre-placement wire length estimation can be a useful tool during the physical design of integrated circuits. In this paper, an a priori wire length estimatio...
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...