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MASS
2010
162views Communications» more  MASS 2010»
15 years 3 months ago
A metric for routing in delay-sensitive wireless sensor networks
Abstract--We present a new scheme to reduce the end-toend routing delay in the mission-critical applications of the wireless sensor networks (WSNs) under the duty cycle model. Whil...
Zhen Jiang, Jie Wu, Risa Ito
MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
15 years 3 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
15 years 3 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
MICRO
2010
IEEE
175views Hardware» more  MICRO 2010»
15 years 3 months ago
Efficient Selection of Vector Instructions Using Dynamic Programming
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...
Rajkishore Barik, Jisheng Zhao, Vivek Sarkar
MICRO
2010
IEEE
270views Hardware» more  MICRO 2010»
15 years 3 months ago
Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
Abstract-- We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficien...
Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim...
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