1396 search results - page 31 / 280 » DATES: Design Analysis Tool for Enterprise Systems |
ISSS
1997
IEEE
15 years 4 months ago
1997
IEEE
This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
116
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DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
101
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DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
Reflection and automated introspection of a design in system level design frameworks are seen as necessities for the CAD tools to manipulate the designs within the tools. These f...
102
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ICECCS
2009
IEEE
14 years 9 months ago
2009
IEEE
In hard real-time systems such as avionics, computer board level designs are typically customized to meet specific reliability and real time requirements. This paper focuses on co...
ICIS
2004
15 years 1 months ago
2004
Although called systems, information systems in organizations are often viewed as tools that "users" use. IS success is often gauged as though it were about acceptance a...