473 search results - page 59 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
ISSS
2002
IEEE
15 years 4 months ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
DAC
2010
ACM
15 years 3 months ago
2010
ACM
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
MOBIHOC
2012
ACM
13 years 2 months ago
2012
ACM
Nowadays, an increasing number of objects can be represented by their wireless electronic identifiers. For example, people can be recognized by their phone numbers or their phone...
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GLVLSI
2008
IEEE
15 years 6 months ago
2008
IEEE
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
ICCAD
2009
IEEE
14 years 9 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...