473 search results - page 68 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
GLVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
ICCAD
2003
IEEE
15 years 8 months ago
2003
IEEE
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
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DAC
2005
ACM
16 years 22 days ago
2005
ACM
Small, embedded integrated circuits (ICs) such as smart cards are vulnerable to so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power co...
DAC
2007
ACM
16 years 23 days ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...