473 search results - page 69 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
ICASSP
2010
IEEE
14 years 12 months ago
2010
IEEE
The widespread availability of photo editing software has made it easy to create visually convincing digital image forgeries. To address this problem, there has been much recent w...
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ISLPED
2003
ACM
15 years 5 months ago
2003
ACM
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
DAC
2009
ACM
15 years 6 months ago
2009
ACM
This paper describes an automatic methodology for optimizing sample point selection for using in the framework of model order reduction (MOR). The procedure, based on the maximiza...
GLVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
GLVLSI
1997
IEEE
15 years 4 months ago
1997
IEEE
In a VHDL-based design flow for applicationspecific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Sta...