473 search results - page 7 / 95 » Design Methodologies for Noise in Digital Integrated Circuit... |
ASPDAC
2008
ACM
15 years 1 months ago
2008
ACM
In this paper, we present a novel design methodology to combat the ever-aggravating high frequency power supply noise (di/dt) in modern microprocessors. Our methodology integrates ...
DAC
2007
ACM
16 years 20 days ago
2007
ACM
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
113
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DAC
2005
ACM
15 years 1 months ago
2005
ACM
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at...
DATE
1997
IEEE
15 years 3 months ago
1997
IEEE
A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to t...