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ISPD
2010
ACM
195views Hardware» more  ISPD 2010»
15 years 6 months ago
Density gradient minimization with coupling-constrained dummy fill for CMP control
In the nanometer IC design, dummy fill is often performed to improve layout pattern uniformity and the post-CMP quality. However, filling dummies might greatly increase intercon...
Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang
DESRIST
2009
Springer
125views Education» more  DESRIST 2009»
15 years 4 months ago
An empirical evaluation of information security awareness levels in designing secure business processes
Information Systems Security (ISS) is critical to ensuring the integrity and credibility of digitally exchanged information in business processes. Information systems development ...
Fergle D'Aubeterre, Lakshmi S. Iyer, Rahul Singh
PATMOS
2007
Springer
15 years 5 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
ICCAD
2004
IEEE
128views Hardware» more  ICCAD 2004»
15 years 8 months ago
Power estimation for cycle-accurate functional descriptions of hardware
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj...
GLVLSI
2009
IEEE
189views VLSI» more  GLVLSI 2009»
15 years 6 months ago
High-performance, cost-effective heterogeneous 3D FPGA architectures
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
Roto Le, Sherief Reda, R. Iris Bahar