279 search results - page 47 / 56 » Design Methodology for Pipelined Heterogeneous Multiprocesso... |
SAC
2006
ACM
15 years 5 months ago
2006
ACM
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
102
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SIGMETRICS
2002
ACM
14 years 11 months ago
2002
ACM
Computer system designers often evaluate future design alternatives with detailed simulators that strive for functional fidelity (to execute relevant workloads) and performance fi...
DSD
2004
IEEE
15 years 3 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
108
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TIP
2008
14 years 11 months ago
2008
Abstract--In this paper, we analyze the computational challenges in implementing particle filtering, especially to video sequences. Particle filtering is a technique used for filte...
102
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RECONFIG
2008
IEEE
15 years 6 months ago
2008
IEEE
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...