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ICCAD
2001
IEEE
153views Hardware» more  ICCAD 2001»
15 years 7 months ago
The Sizing Rules Method for Analog Integrated Circuit Design
This paper presents the sizing rules method for analog CMOS circuit design that consists of: first, the development of a hierarchical library of transistor pair groups as basic b...
Helmut E. Graeb, Stephan Zizala, Josef Eckmueller,...
ATS
2005
IEEE
98views Hardware» more  ATS 2005»
15 years 4 months ago
Untestable Multi-Cycle Path Delay Faults in Industrial Designs
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
Manan Syal, Michael S. Hsiao, Suriyaprakash Natara...
ESEM
2008
ACM
15 years 17 days ago
Are good code reviewers also good at design review?
Software review is a necessity activity to build high reliability software in software development. In this paper, we experimentally analyze the difference in performance between ...
Hidetake Uwano, Akito Monden, Ken-ichi Matsumoto
ISLPED
2007
ACM
94views Hardware» more  ISLPED 2007»
15 years 10 days ago
Design of an efficient power delivery network in an soc to enable dynamic power management
Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabl...
Behnam Amelifard, Massoud Pedram
SEDE
2007
15 years 6 days ago
Case study: A tool centric approach for fault avoidance in microchip designs
— Achieving reliability in fault tolerant systems requires both avoidance and redundancy. This study focuses on avoidance as it pertains to the design of microchips. The lifecycl...
Clemente Izurieta