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TVLSI
2008
99views more  TVLSI 2008»
15 years 5 months ago
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
Sheng-Chih Lin, Kaustav Banerjee
ICCD
2003
IEEE
147views Hardware» more  ICCD 2003»
16 years 2 months ago
Design Flow Enhancements for DNA Arrays
DNA probe arrays have recently emerged as one of the core genomic technologies. Exploiting analogies between manufacturing processes for DNA arrays and for VLSI chips, we demonstr...
Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu ...
IPPS
2009
IEEE
16 years 20 days ago
Understanding the design trade-offs among current multicore systems for numerical computations
In this paper, we empirically evaluate fundamental design trade-offs among the most recent multicore processors and accelerator technologies. Our primary aim is to aid application...
Seunghwa Kang, David A. Bader, Richard W. Vuduc
NOCS
2007
IEEE
16 years 8 days ago
NoC Design and Implementation in 65nm Technology
As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent...
Antonio Pullini, Federico Angiolini, Paolo Meloni,...
ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
15 years 12 months ago
An automated design flow for 3D microarchitecture evaluation
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Re...