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ISLPED
1999
ACM
177views Hardware» more  ISLPED 1999»
15 years 9 months ago
Low power synthesis of dual threshold voltage CMOS VLSI circuits
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
Vijay Sundararajan, Keshab K. Parhi
CORR
2007
Springer
120views Education» more  CORR 2007»
15 years 5 months ago
On the Feedback Capacity of Power Constrained Gaussian Noise Channels with Memory
—For a stationary additive Gaussian-noise channel with a rational noise power spectrum of a finite-order L, we derive two new results for the feedback capacity under an average ...
Shaohua Yang, Aleksandar Kavcic, Sekhar Tatikonda
VTC
2010
IEEE
404views Communications» more  VTC 2010»
15 years 3 months ago
Power Efficient Dynamic Resource Scheduling Algorithms for LTE
: This paper presents a link level analysis of the rate and energy efficiency performance of the LTE downlink considering the unitary codebook based precoding scheme. In a multi-us...
Congzheng Han, Kian Chung Beh, Marios Nicolaou, Si...
ISQED
2006
IEEE
106views Hardware» more  ISQED 2006»
15 years 11 months ago
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
ISLPED
1995
ACM
131views Hardware» more  ISLPED 1995»
15 years 9 months ago
Guarded evaluation: pushing power management to logic synthesis/design
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
Vivek Tiwari, Sharad Malik, Pranav Ashar