710 search results - page 35 / 142 » Estimating design time for system circuits |
DATE
2000
IEEE
15 years 4 months ago
2000
IEEE
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
BMCBI
2005
14 years 11 months ago
2005
Background: Gene expression programs depend on recognition of cis elements in promoter region of target genes by transcription factors (TFs), but how TFs regulate gene expression ...
DAC
2005
ACM
16 years 23 days ago
2005
ACM
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...
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ICASSP
2009
IEEE
15 years 3 months ago
2009
IEEE
In this paper, we investigate the timing and carrier frequency offset (CFO) synchronization problem in decode and forward cooperative systems operating over frequency selective ch...
RTAS
2005
IEEE
15 years 5 months ago
2005
IEEE
During real-world design of embedded real-time systems, it cannot be expected that all performance data required for scheduling analysis is fully available up front. In such situa...