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ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
15 years 4 months ago
Hierarchical Interconnect Circuit Models
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...
ERSA
2010
187views Hardware» more  ERSA 2010»
14 years 9 months ago
An Open Source Circuit Library with Benchmarking Facilities
In this paper, we introduce the open-source PivPav backend tool for reconfigurable computing. Essentially, PivPav provides an interface to a library of digital circuits that are ke...
Mariusz Grad, Christian Plessl
ICCAD
1993
IEEE
121views Hardware» more  ICCAD 1993»
15 years 3 months ago
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
Arjan J. van Genderen, N. P. van der Meijs
ISCAS
2008
IEEE
120views Hardware» more  ISCAS 2008»
15 years 6 months ago
Improving the power-delay product in SCL circuits using source follower output stage
— This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay...
Armin Tajalli, Frank K. Gürkaynak, Yusuf Lebl...
DAC
1989
ACM
15 years 3 months ago
An Efficient Finite Element Method for Submicron IC Capacitance Extraction
We present an accurate and efficient method for extraction of parasitic capacitances in submicron integrated circuits. The method uses a 3-D finite element model in which the cond...
N. P. van der Meijs, Arjan J. van Genderen