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ISLPED
1996
ACM
103views Hardware» more  ISLPED 1996»
15 years 3 months ago
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving
This paper proposes a 0.5V / 100MHz / sub-5mW-operated 1-Mbit SRAM cell architecture which uses an overVCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimi...
Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, ...
CHINAF
2006
110views more  CHINAF 2006»
14 years 11 months ago
Time-domain analysis methodology for large-scale RLC circuits and its applications
: With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical d...
Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong ...
ISMVL
2003
IEEE
83views Hardware» more  ISMVL 2003»
15 years 5 months ago
Multiple-Valued Dynamic Source-Coupled Logic
A new multiple-valued current-mode (MVCM) integrated circuit based on dynamic source-coupled logic (SCL) is proposed for low-power VLSI applications. The use of a precharge-evalua...
Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyam...
STOC
2005
ACM
150views Algorithms» more  STOC 2005»
16 years 5 hour ago
Correcting errors without leaking partial information
This paper explores what kinds of information two parties must communicate in order to correct errors which occur in a shared secret string W. Any bits they communicate must leak ...
Yevgeniy Dodis, Adam Smith
FOCS
1999
IEEE
15 years 4 months ago
Near-Optimal Conversion of Hardness into Pseudo-Randomness
Various efforts ([?, ?, ?]) have been made in recent years to derandomize probabilistic algorithms using the complexity theoretic assumption that there exists a problem in E = dti...
Russell Impagliazzo, Ronen Shaltiel, Avi Wigderson