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ANCS
2007
ACM
15 years 9 months ago
Experimenting with buffer sizes in routers
Recent theoretical results in buffer sizing research suggest that core Internet routers can achieve high link utilization, if they are capable of storing only a handful of packets...
Neda Beheshti, Jad Naous, Yashar Ganjali, Nick McK...
CF
2007
ACM
15 years 9 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
CHES
2006
Springer
179views Cryptology» more  CHES 2006»
15 years 9 months ago
Offline Hardware/Software Authentication for Reconfigurable Platforms
Abstract. Many Field-Programmable Gate Array (FPGA) based systems utilize third-party intellectual property (IP) in their development. When they are deployed in non-networked envir...
Eric Simpson, Patrick Schaumont
FCCM
2004
IEEE
103views VLSI» more  FCCM 2004»
15 years 9 months ago
A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder
The development of turbo codes has allowed for nearShannon limit information transfer in modern communication systems. Although turbo decoding is viewed as superior to alternate d...
Jian Liang, Russell Tessier, Dennis Goeckel
FPL
2006
Springer
120views Hardware» more  FPL 2006»
15 years 9 months ago
Regular Expression Software Deceleration for Intrusion Detection Systems
The use of reconfigurable hardware for network security applications has recently made great strides as FPGA devices have provided larger and faster resources. Regular expressions...
Zachary K. Baker, Viktor K. Prasanna, Hong-Jip Jun...