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ALIFE
2002
15 years 5 months ago
An Interactive Self-Replicator Implemented in Hardware
Self-replicating loops presented to date are essentially worlds unto themselves, inaccessible to the observer once the replication process is launched. In this article we present t...
André Stauffer, Moshe Sipper
ANNS
2010
15 years 4 months ago
A Software Framework for Mapping Neural Networks to a Wafer-scale Neuromorphic Hardware System
In this contribution we will provide the reader with outcomes of the development of a novel software framework for an unique wafer-scale neuromordware system. The hardware system i...
Matthias Ehrlich, Karsten Wendt, Lukas Zühl, ...
VIS
2006
IEEE
214views Visualization» more  VIS 2006»
16 years 7 months ago
Hub-based Simulation and Graphics Hardware Accelerated Visualization for Nanotechnology Applications
The Network for Computational Nanotechnology (NCN) has developed a science gateway at nanoHUB.org for nanotechnology education and research. Remote users can browse through online...
Wei Qiao, Michael McLennan, Rick Kennell, David...
ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
16 years 2 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
AOSD
2009
ACM
16 years 25 days ago
Modelling hardware verification concerns specified in the e language: an experience report
e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In rec...
Darren Galpin, Cormac Driver, Siobhán Clark...