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CODES
2003
IEEE
15 years 10 months ago
Accurate estimation of cache-related preemption delay
Multitasked real-time systems often employ caches to boost performance. However the unpredictable dynamic behavior of caches makes schedulability analysis of such systems difficul...
Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudh...
CODES
2003
IEEE
15 years 10 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
CODES
2003
IEEE
15 years 10 months ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...
EUROMICRO
2003
IEEE
15 years 10 months ago
Web Service Composition Languages: Old Wine in New Bottles?
Recently, several languages for web service composition have emerged (e.g., BPEL4WS and WSCI). The goal of these languages is to glue web services together in a process-oriented w...
Wil M. P. van der Aalst, Marlon Dumas, Arthur H. M...
GLVLSI
2003
IEEE
130views VLSI» more  GLVLSI 2003»
15 years 10 months ago
Zero overhead watermarking technique for FPGA designs
FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing w...
Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu
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