Existing DRAM controllers employ rigid, non-adaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetch requests the same ...
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
— The recent investigations on interleave-division multiple-access (IDMA) have demonstrated its advantage in supporting high-data-rate and multi-rate services over wireless fadin...
Qian Huang, Sammy Chan, King-Tim Ko, Li Ping, Peng...
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...
—Duty-cycle MAC protocols have been proposed to meet the demanding energy requirements of wireless sensor networks. Although existing duty-cycle MAC protocols such as S-MAC are p...