1001 search results - page 25 / 201 » Improving memory hierarchy performance for irregular applica... |
121
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IPPS
2005
IEEE
15 years 5 months ago
2005
IEEE
The problem of writing high performance parallel applications becomes even more challenging when irregular, sparse or adaptive methods are employed. In this paper we introduce com...
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
– In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhan...
IPPS
2010
IEEE
14 years 9 months ago
2010
IEEE
Increasing the core-count on current and future processors is posing critical challenges to the memory subsystem to efficiently handle concurrent memory requests. The current tren...
92
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TPDS
2010
14 years 10 months ago
2010
The circular sensing model has been widely used to estimate performance of sensing applications in existing analysis and simulations. While this model provides valuable high-level...
107
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IPPS
2010
IEEE
14 years 9 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...