552 search results - page 90 / 111 » Low power techniques for Motion Estimation hardware |
CODES
2008
IEEE
15 years 6 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
101
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CGO
2004
IEEE
15 years 3 months ago
2004
IEEE
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
FGIT
2009
Springer
15 years 6 months ago
2009
Springer
GRID environments are privileged targets for computation-intensive problem solving in areas from weather forecasting to seismic analysis. Mainly composed by commodity hardware, th...
103
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IEEEPACT
2002
IEEE
15 years 4 months ago
2002
IEEE
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract—Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) d...