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» Low power techniques for Motion Estimation hardware
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GLVLSI
2008
IEEE
140views VLSI» more  GLVLSI 2008»
15 years 6 months ago
A table-based method for single-pass cache optimization
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank V...
IEEEPACT
2009
IEEE
15 years 6 months ago
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading
Industry is moving towards multi-core designs as we have hit the memory and power walls. Multi-core designs are very effective to exploit thread-level parallelism (TLP) but do not...
Carlos Madriles, Pedro López, Josep M. Codi...
ICCAD
2007
IEEE
103views Hardware» more  ICCAD 2007»
15 years 8 months ago
Enhancing design robustness with reliability-aware resynthesis and logic simulation
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov,...
GECCO
2004
Springer
148views Optimization» more  GECCO 2004»
15 years 5 months ago
A Multi-objective Approach to Configuring Embedded System Architectures
Portable embedded systems are being driven by consumer demands to be thermally efficient, perform faster, and have longer battery life. To design such a system, various hardware un...
James Northern III, Michael A. Shanblatt
ISCAS
2003
IEEE
98views Hardware» more  ISCAS 2003»
15 years 5 months ago
Minimum selection GSC and adaptive low-power rake combining scheme
In this paper, we investigate a new generalized selection combining (GSC) technique and an adaptive rake combining scheme to save the power consumption of mobile rake receivers fo...
Suk Won Kim, Dong Sam Ha, Jeffrey H. Reed