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» Low power techniques for Motion Estimation hardware
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DATE
2010
IEEE
168views Hardware» more  DATE 2010»
15 years 4 months ago
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
Luca Sterpone, Niccolò Battezzati
DATE
2010
IEEE
158views Hardware» more  DATE 2010»
15 years 4 months ago
Energy- and endurance-aware design of phase change memory caches
—Phase change memory (PCM) is one of the most promising technology among emerging non-volatile random access memory technologies. Implementing a cache memory using PCM provides m...
Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun,...
SIGMETRICS
2011
ACM
161views Hardware» more  SIGMETRICS 2011»
14 years 2 months ago
Modeling program resource demand using inherent program characteristics
The workloads in modern Chip-multiprocessors (CMP) are becoming increasingly diversified, creating different resource demands on hardware substrate. It is necessary to allocate h...
Jian Chen, Lizy Kurian John, Dimitris Kaseridis
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 5 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
ICCAD
2002
IEEE
112views Hardware» more  ICCAD 2002»
15 years 4 months ago
ATPG-based logic synthesis: an overview
The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is exp...
Chih-Wei Jim Chang, Malgorzata Marek-Sadowska