552 search results - page 96 / 111 » Low power techniques for Motion Estimation hardware |
103
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ICCD
2008
IEEE
15 years 6 months ago
2008
IEEE
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
102
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SIPS
2008
IEEE
15 years 6 months ago
2008
IEEE
Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power pe...
APCCAS
2002
IEEE
15 years 4 months ago
2002
IEEE
This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as ...
DAC
2004
ACM
16 years 20 days ago
2004
ACM
Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio...
91
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GLVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...