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» Mapping Applications to a Coarse Grain Reconfigurable System
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DATE
2003
IEEE
90views Hardware» more  DATE 2003»
15 years 5 months ago
Mapping Applications to an FPFA Tile
Abstract— This paper introduces a transformational design method which can be used to map code written in a high level source language, like C, to a coarse grain reconfigurable ...
Michèl A. J. Rosien, Yuanqing Guo, Gerard J...
ERSA
2009
147views Hardware» more  ERSA 2009»
14 years 9 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
ISCAS
2005
IEEE
125views Hardware» more  ISCAS 2005»
15 years 5 months ago
A methodology for partitioning DSP applications in hybrid reconfigurable systems
—In this paper, we describe an automated and formalized methodology for partitioning computational intensive applications between reconfigurable hardware blocks of different gran...
Michalis D. Galanis, Athanasios Milidonis, George ...
MJ
2006
145views more  MJ 2006»
14 years 11 months ago
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
Michalis D. Galanis, Athanasios Milidonis, Athanas...
FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
14 years 3 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...