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» Mechanisms for store-wait-free multiprocessors
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GLVLSI
2007
IEEE
211views VLSI» more  GLVLSI 2007»
15 years 6 months ago
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip
Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power densi...
Salvatore Carta, Andrea Acquaviva, Pablo Garcia De...
ACMICEC
2007
ACM
201views ECommerce» more  ACMICEC 2007»
15 years 3 months ago
Bid based scheduler with backfilling for a multiprocessor system
We consider a virtual computing environment that provides computational resources on demand to users with multiattribute task descriptions that include a valuation, resource (CPU)...
Inbal Yahav, Louiqa Raschid, Henrique Andrade
IISWC
2006
IEEE
15 years 5 months ago
Modeling Cache Sharing on Chip Multiprocessor Architectures
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...
Pavlos Petoumenos, Georgios Keramidas, Håkan...
IPPS
2007
IEEE
15 years 6 months ago
Scaling and Packing on a Chip Multiprocessor
Power management is critical in server and high-performancecomputing environments as well as in mobile computing. Many mechanisms have been developed over recent years to support ...
Vincent W. Freeh, Tyler K. Bletsch, Freeman L. Raw...
ISCA
1994
IEEE
104views Hardware» more  ISCA 1994»
15 years 3 months ago
Exploring the Design Space for a Shared-Cache Multiprocessor
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
Basem A. Nayfeh, Kunle Olukotun