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» Mechanisms for store-wait-free multiprocessors
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DAC
1996
ACM
15 years 4 months ago
Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems
In this paper we present an integrated simulation paradigm in which parallel mixed-mode co-simulation is accomplished by integrating sequential simulators in a software simulation ...
Antonio R. W. Todesco, Teresa H. Y. Meng
PARLE
1994
15 years 3 months ago
Using Reference Counters in Update-Based Coherent Memory
Abstract. As the disparity between processor and memory speed continues to widen, the exploitation of locality of reference in shared-memory multiprocessors becomes an increasingly...
Evangelos P. Markatos, Catherine E. Chronaki
ICFP
2009
ACM
16 years 13 days ago
Parallel concurrent ML
Concurrent ML (CML) is a high-level message-passing language that supports the construction of first-class synchronous abstractions called events. This mechanism has proven quite ...
John H. Reppy, Claudio V. Russo, Yingqi Xiao
RTSS
2005
IEEE
15 years 5 months ago
Enhancing the Robustness of Distributed Real-Time Middleware via End-to-End Utilization Control
A key challenge for distributed real-time and embedded (DRE) middleware is maintaining both system reliability and desired real-time performance in unpredictable environments wher...
Xiaorui Wang, Chenyang Lu, Xenofon D. Koutsoukos
WDAG
2004
Springer
98views Algorithms» more  WDAG 2004»
15 years 5 months ago
Dynamic Memory ABP Work-Stealing
The non-blocking work-stealing algorithm of Arora, Blumofe, and Plaxton (hencheforth ABP work-stealing) is on its way to becoming the multiprocessor load balancing technology of ch...
Danny Hendler, Yossi Lev, Nir Shavit