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DATE
2010
IEEE
138views Hardware» more  DATE 2010»
15 years 10 months ago
Checking and deriving module paths in Verilog cell library descriptions
—Module paths are often used to specify the delays of cells in a Verilog cell library description, which define the propagation delay for an event from an input to an output. Sp...
Matthias Raffelsieper, Mohammad Reza Mousavi, Chri...
WOODPECKER
2001
15 years 6 months ago
Consistency Checking of RM-ODP Specifications
Ensuring that specifications are consistent is an important part of specification development and testing. In this paper we introduce the ConsVISor tool for consistency checking o...
Kenneth Baclawski, Mieczyslaw M. Kokar, Jeffrey E....
ENTCS
2008
105views more  ENTCS 2008»
15 years 5 months ago
Checking Equivalence for Reo Networks
Constraint automata have been used as an operational model for component connectors described in the coordination language Reo which specifies the cooperation and communication of...
Tobias Blechmann, Christel Baier
ICDE
2006
IEEE
152views Database» more  ICDE 2006»
16 years 6 months ago
U-Filter: A Lightweight XML View Update Checker
Updates over virtual XML views that wrap relational data are not well supported by XML data management systems. This paper studies the problem of whether a correct relational upda...
Ling Wang, Elke A. Rundensteiner, Murali Mani
CGO
2009
IEEE
16 years 9 days ago
Fast Track: A Software System for Speculative Program Optimization
—Fast track is a software speculation system that enables unsafe optimization of sequential code. It speculatively runs optimized code to improve performance and then checks the ...
Kirk Kelsey, Tongxin Bai, Chen Ding, Chengliang Zh...