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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 7 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
ASPLOS
2008
ACM
15 years 7 months ago
Accurate branch prediction for short threads
Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to e...
Bumyong Choi, Leo Porter, Dean M. Tullsen
ASWEC
2008
IEEE
15 years 7 months ago
Embedding Architectural Practices into Extreme Programming
Today, agile methods become a popular approach to develop software systems. They try to satisfy customer, respond to changes, release in less time and achieve suitable profits for...
Amir Azim Sharifloo, Amir S. Saffarian, Fereidoon ...
ATAL
2008
Springer
15 years 7 months ago
An agent-based electrical power market
This demonstration shows an agent-based model for the electricity power market, in which the optimal power flow is determined in a bottom-up fashion. Here, each agent controls a s...
Jaime Cerda Jacobo, David De Roure, Enrico H. Gerd...
CEAS
2008
Springer
15 years 7 months ago
Personalized Spam Filtering for Gray Mail
Gray mail, messages that could reasonably be considered either spam or good by different email users, is a commonly observed issue in production spam filtering systems. In this pa...
Ming-Wei Chang, Scott Yih, Robert McCann
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