129 search results - page 16 / 26 » Novel Design Methodology for High-Performance XOR-XNOR Circu... |
102
Voted
ASPDAC
2005
ACM
15 years 1 months ago
2005
ACM
— Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to...
81
Voted
ICCAD
2008
IEEE
15 years 8 months ago
2008
IEEE
—Hardware Intellectual Property (IP) cores have emerged as an integral part of modern System–on–Chip (SoC) designs. However, IP vendors are facing major challenges to protect...
59
Voted
ISQED
2008
IEEE
15 years 6 months ago
2008
IEEE
— Designers require variational information for robust designs. Characterization of such information can be costly for the novel nanoparticle interconnect process, which utilize ...
113
Voted
DAC
2005
ACM
15 years 1 months ago
2005
ACM
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
ISSS
2002
IEEE
15 years 4 months ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...