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CAL
2007
14 years 12 months ago
Microarchitectures for Managing Chip Revenues under Process Variations
—As transistor feature sizes continue to shrink into the sub-90nm range and beyond, the effects of process variations on critical path delay and chip yields have amplified. A com...
Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph...
ICS
1998
Tsinghua U.
15 years 4 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
102
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EUROPAR
2010
Springer
15 years 1 months ago
Thread Owned Block Cache: Managing Latency in Many-Core Architecture
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
Fenglong Song, Zhiyong Liu, Dongrui Fan, Hao Zhang...
CCS
2007
ACM
15 years 4 months ago
Highly efficient techniques for network forensics
Given a history of packet transmissions and an excerpt of a possible packet payload, the payload attribution problem requires the identification of sources, destinations and the t...
Miroslav Ponec, Paul Giura, Hervé Brön...
ICB
2007
Springer
164views Biometrics» more  ICB 2007»
15 years 3 months ago
Hardening Fingerprint Fuzzy Vault Using Password
Security of stored templates is a critical issue in biometric systems because biometric templates are non-revocable. Fuzzy vault is a cryptographic framework that enables secure te...
Karthik Nandakumar, Abhishek Nagar, Anil K. Jain