301 search results - page 36 / 61 » On bounding the delay of a critical path |
GLVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
ISPD
1999
ACM
15 years 4 months ago
1999
ACM
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
103
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FPL
2006
Springer
15 years 3 months ago
2006
Springer
We introduce a new congestion driven placement algorithm for FPGAs in which the overlappingeffect of boundingboxes is taken into consideration. Experimental results show that comp...
ASPDAC
2005
ACM
15 years 1 months ago
2005
ACM
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
114
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GLOBECOM
2010
IEEE
14 years 9 months ago
2010
IEEE
Abstract--Proper admission control in cognitive radio networks is critical in providing QoS guarantees to secondary unlicensed users. In this paper, we study the admission control ...