3742 search results - page 39 / 749 » On the Use of Formal Techniques for Validation |
DAC
2003
ACM
16 years 22 days ago
2003
ACM
We describe a technique for verifying that a hardware design correctly implements a protocol-level formal specification. Simulation steps are translated to protocol state transiti...
ICRA
2008
IEEE
15 years 6 months ago
2008
IEEE
— In this paper, we lay the groundwork for extending our previously developed ASyMTRe architecture to enable constructivist learning for multi-robot team tasks. The ASyMTRe archi...
MICCAI
2005
Springer
16 years 20 days ago
2005
Springer
In this paper, we present an evaluation of seven automatic brain tissue classifiers based on level of agreements. A number of agreement measures are explained, and we show how they...
ICC
2007
IEEE
15 years 6 months ago
2007
IEEE
— An interferometric ranging technique has been recently proposed as a possible way to localize ad hoc and sensor networks. Compared to the more common techniques such as receive...
VLSID
2002
IEEE
16 years 4 days ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...