1912 search results - page 353 / 383 » Optimizing interconnection policies |
101
click to vote
ICCAD
2006
IEEE
16 years 2 months ago
2006
IEEE
Most existing buffering algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches...
142
click to vote
ICCAD
2001
IEEE
16 years 2 months ago
2001
IEEE
In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal trans...
158
click to vote
SOSP
2009
ACM
16 years 2 months ago
2009
ACM
Commodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instructio...
168
click to vote
FPGA
2010
ACM
16 years 2 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
152
click to vote
MICRO
2009
IEEE
16 years 4 days ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...