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EUROPAR
2009
Springer
15 years 10 months ago
MyriXen: Message Passing in Xen Virtual Machines over Myrinet and Ethernet
Data access in HPC infrastructures is realized via user-level networking and OS-bypass techniques through which nodes can communicate with high bandwidth and low-latency. Virtualiz...
Anastassios Nanos, Nectarios Koziris
ICCAD
2000
IEEE
109views Hardware» more  ICCAD 2000»
15 years 10 months ago
Latency-Guided On-Chip Bus Network Design
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
Milenko Drinic, Darko Kirovski, Seapahn Meguerdich...
SPAA
1993
ACM
15 years 9 months ago
Supporting Sets of Arbitrary Connections on iWarp Through Communication Context Switches
In this paper we introduce the ConSet communication model for distributed memory parallel computers. The communication needs of an application program can be satisfied by some ar...
Anja Feldmann, Thomas Stricker, Thomas E. Warfel
CODES
2004
IEEE
15 years 9 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
FOCS
1995
IEEE
15 years 9 months ago
Disjoint Paths in Densely Embedded Graphs
We consider the following maximum disjoint paths problem (mdpp). We are given a large network, and pairs of nodes that wish to communicate over paths through the network — the g...
Jon M. Kleinberg, Éva Tardos