619 search results - page 25 / 124 » Oversubscription on multicore processors |
101
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ISCA
2009
IEEE
15 years 6 months ago
2009
IEEE
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
CF
2009
ACM
15 years 6 months ago
2009
ACM
As we reach the limits of single-core computing, we are promised more and more cores in our systems. Modern architectures include many performance counters per core, but few or no...
106
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ICPP
2008
IEEE
15 years 6 months ago
2008
IEEE
This paper describes a generalisation of modulo scheduling to parallelise loops for SpMT processors that exploits simultaneously both instruction-level parallelism and thread-leve...
115
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IEEEPACT
2007
IEEE
15 years 6 months ago
2007
IEEE
Many sorting algorithms have been studied in the past, but there are only a few algorithms that can effectively exploit both SIMD instructions and threadlevel parallelism. In this...
CC
2005
Springer
15 years 5 months ago
2005
Springer
Abstract. Network processors (NPs) typically contain multiple concurrent processing cores. State-of-the-art programming techniques for NPs are invariably low-level, requiring progr...