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DPHOTO
2010
176views Hardware» more  DPHOTO 2010»
15 years 1 months ago
Low-cost space-varying FIR filter architecture for computational imaging systems
Recent research demonstrates the advantage of designing electro-optical imaging systems by jointly optimizing the optical and digital subsystems. The optical systems designed usin...
Guotong Feng, Mohammed Shoaib, Edward L. Schwartz,...
TPDS
2008
134views more  TPDS 2008»
14 years 11 months ago
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
Ricardo Fernández Pascual, José M. G...
WMPI
2004
ACM
15 years 5 months ago
A case for multi-level main memory
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
Magnus Ekman, Per Stenström
ICCAD
2003
IEEE
325views Hardware» more  ICCAD 2003»
15 years 5 months ago
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
Brian Swahn, Soha Hassoun
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
15 years 4 months ago
CMOS system-on-a-chip voltage scaling beyond 50nm
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoo...