Sciweavers

1238 search results - page 207 / 248
» Power Efficient Processor Architecture and The Cell Processo...
Sort
View
MOBISYS
2003
ACM
15 years 11 months ago
Service-Oriented Network Sockets
3], in that it integrates a service-oriented abstraction with the operating system socket interface and provides adaptive service access at the end-host session layer. However, our...
Umar Saif, Justin Mazzola Paluska
LCTRTS
1999
Springer
15 years 4 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...
APCSAC
2004
IEEE
15 years 3 months ago
Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory. This paper is a first look at the value of RAMpage to ...
Philip Machanick
DAC
2005
ACM
15 years 1 months ago
Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
Antonio Carlos Schneider Beck, Luigi Carro
SIGCOMM
2009
ACM
15 years 6 months ago
PLUG: flexible lookup modules for rapid deployment of new protocols in high-speed routers
New protocols for the data link and network layer are being proposed to address limitations of current protocols in terms of scalability, security, and manageability. High-speed r...
Lorenzo De Carli, Yi Pan, Amit Kumar, Cristian Est...