Sciweavers

1238 search results - page 41 / 248
» Power Efficient Processor Architecture and The Cell Processo...
Sort
View
DATE
2005
IEEE
134views Hardware» more  DATE 2005»
15 years 5 months ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
DATE
2000
IEEE
113views Hardware» more  DATE 2000»
15 years 4 months ago
Static Timing Analysis of Embedded Software on Advanced Processor Architectures
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...
André Hergenhan, Wolfgang Rosenstiel
CPHYSICS
2011
200views Education» more  CPHYSICS 2011»
14 years 6 months ago
Adaptable Particle-in-Cell algorithms for graphical processing units
We developed new parameterized Particle-in-Cell algorithms and data structures for emerging multi-core and many-core architectures. Four parameters allow tuning of this PIC code t...
Viktor K. Decyk, Tajendra V. Singh
FPGA
2006
ACM
98views FPGA» more  FPGA 2006»
15 years 3 months ago
Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic
Abstract-- Increasing device densities allow chip manufacturers to integrate more functionality onto a single piece of silicon. FPGA manufacturers, such as Xilinx and Altera, use t...
Joshua Noseworthy, Miriam Leeser
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
16 years 2 days ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...