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IPPS
2005
IEEE
15 years 5 months ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
EUROPAR
2008
Springer
15 years 1 months ago
Radioastronomy Image Synthesis on the Cell/B.E.
Abstract. Now that large radiotelescopes like SKA, LOFAR, or ASKAP, become available in different parts of the world, radioastronomers foresee a vast increase in the amount of data...
Ana Lucia Varbanescu, Alexander S. van Amesfoort, ...
ISCA
1996
IEEE
102views Hardware» more  ISCA 1996»
15 years 4 months ago
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, He...
DAC
1998
ACM
16 years 22 days ago
A Video Signal Processor for MIMD Multiprocessing
The video signal processor AxPe1280V has been developed for implementation of different video coding applications according to standards like ITU-T H.261/H.263, and ISO MPEG-1/2. ...
Dirk Niggemeyer, Jörg Hilgenstock, Jan Otters...
HPCA
2011
IEEE
14 years 3 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...