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SAC
2006
ACM
15 years 5 months ago
Branchless cycle prediction for embedded processors
Modern embedded processors access the Branch Target Buffer (BTB) every cycle to speculate branch target addresses. Such accesses, quite often, are unnecessary as there is no branc...
Kaveh Jokar Deris, Amirali Baniasadi
RCC
2002
104views more  RCC 2002»
14 years 11 months ago
Architectural Specification, Exploration and Simulation Through Rewriting-Logic
In recent years Arvind's Group at MIT has shown the usefulness of term rewriting theory for the specification of processor architectures. In their approach processors specifi...
Mauricio Ayala-Rincón, Reiner W. Hartenstei...
PPOPP
2006
ACM
15 years 5 months ago
High-performance IPv6 forwarding algorithm for multi-core and multithreaded network processor
IP forwarding is one of the main bottlenecks in Internet backbone routers, as it requires performing the longest-prefix match at 10Gbps speed or higher. IPv6 forwarding further ex...
Xianghui Hu, Xinan Tang, Bei Hua
ASAP
2006
IEEE
108views Hardware» more  ASAP 2006»
15 years 3 months ago
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding
State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for ...
Pablo Ituero, Marisa López-Vallejo
WWW
2009
ACM
16 years 14 days ago
Using graphics processors for high performance IR query processing
Web search engines are facing formidable performance challenges as they need to process thousands of queries per second over billions of documents. To deal with this heavy workloa...
Shuai Ding, Jinru He, Hao Yan, Torsten Suel