1238 search results - page 64 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
316
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DAC
2012
ACM
13 years 2 months ago
2012
ACM
Much recent research [8, 6, 7] suggests significant power and energy benefits of relaxing correctness constraints in future processors. Such processors with relaxed constraints ...
DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract—Future microprocessors increasingly rely on an unreliable CMOS fabric due to aggressive scaling of voltage and frequency, and shrinking design margins. Fortunately, many...
100
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GLOBECOM
2007
IEEE
15 years 6 months ago
2007
IEEE
— In this paper, we propose a novel supernode caching scheme to reduce IP lookup latencies and energy consumption in network processors. In stead of using an expensive TCAM based...
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
Software implementations of channel decoding algorithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibil...
112
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ICCAD
1998
IEEE
15 years 4 months ago
1998
IEEE
We consider the problem of scheduling the mixed workload of both sporadic (on-line) and periodic (off-line) tasks on variable voltage processor to optimize power consumption while...