1238 search results - page 65 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
IEEEPACT
2008
IEEE
15 years 6 months ago
2008
IEEE
We design and implement Mars, a MapReduce framework, on graphics processors (GPUs). MapReduce is a distributed programming framework originally proposed by Google for the ease of ...
115
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FPL
2006
Springer
15 years 3 months ago
2006
Springer
The recent development of Platform-FPGA or FieldProgrammable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potent...
101
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HPCA
2009
IEEE
16 years 10 days ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
105
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MICRO
2000
IEEE
14 years 11 months ago
2000
IEEE
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
103
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HPCA
2005
IEEE
16 years 4 days ago
2005
IEEE
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...