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DATE
2009
IEEE
101views Hardware» more  DATE 2009»
15 years 6 months ago
A monitor interconnect and support subsystem for multicore processors
Abstract— In many current SoCs, the architectural interface to onchip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a...
Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burl...
ISCC
2006
IEEE
123views Communications» more  ISCC 2006»
15 years 5 months ago
WISENEP: A Network Processor for Wireless Sensor Networks
Abstract— Wireless sensor networks are ad hoc networks comprised mainly of small sensor nodes with limited resources and one or more base stations, which are much more powerful l...
Andre Mota, Leonardo B. Oliveira, Felipe F. Rocha,...
DATE
2006
IEEE
195views Hardware» more  DATE 2006»
15 years 5 months ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll
JCP
2007
181views more  JCP 2007»
14 years 11 months ago
Reducing Energy Consumption of Wireless Sensor Networks through Processor Optimizations
When the environmental conditions are stable, a typical Wireless Sensor Network (WSN) application may sense and process very similar or constant data values for long durations. Thi...
Gürhan Küçük, Can Basaran
CASES
2009
ACM
15 years 6 months ago
An accelerator-based wireless sensor network processor in 130nm CMOS
Networks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Over the...
Mark Hempstead, Gu-Yeon Wei, David Brooks