1238 search results - page 69 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
101
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ARITH
2001
IEEE
15 years 3 months ago
2001
IEEE
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
107
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EGH
2004
Springer
15 years 5 months ago
2004
Springer
The real time 3D graphics becomes one of the attractive applications for 3G wireless terminals although their battery lifetime and memory bandwidth limit the system resources for ...
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—More and more processor manufacturers have launched embedded multicore processors for consumer electronics products because such processors provide high performance and low powe...
APCSAC
2004
IEEE
15 years 3 months ago
2004
IEEE
Abstract. While the fetch unit has been identified as one of the major bottlenecks of Simultaneous Multithreading architecture, several fetch schemes were proposed by prior works t...
JCP
2008
14 years 11 months ago
2008
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...