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» Power management in external memory using PA-CDRAM
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CASES
2010
ACM
14 years 9 months ago
Balancing memory and performance through selective flushing of software code caches
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...
Apala Guha, Kim M. Hazelwood, Mary Lou Soffa
JUCS
2007
122views more  JUCS 2007»
14 years 11 months ago
A New Architecture for Concurrent Lazy Cyclic Reference Counting on Multi-Processor Systems
: Multi-processor systems have become the standard in current computer architectures. Software developers have the possibility to take advantage of the additional computing power a...
Andrei de Araújo Formiga, Rafael Dueire Lin...
HIPC
2000
Springer
15 years 3 months ago
Meta-data Management System for High-Performance Large-Scale Scientific Data Access
Many scientific applications manipulate large amount of data and, therefore, are parallelized on high-performance computing systems to take advantage of their computational power a...
Wei-keng Liao, Xiaohui Shen, Alok N. Choudhary
PPOPP
2006
ACM
15 years 5 months ago
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hu...
EMSOFT
2009
Springer
15 years 6 months ago
Implementing time-predictable load and store operations
Scratchpads have been widely proposed as an alternative to caches for embedded systems. Advantages of scratchpads include reduced energy consumption in comparison to a cache and a...
Jack Whitham, Neil C. Audsley