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» Power management in external memory using PA-CDRAM
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HPCA
2006
IEEE
16 years 1 days ago
Phase characterization for power: evaluating control-flow-based and event-counter-based techniques
Computer systems increasingly rely on dynamic, phasebased system management techniques, in which system hardware and software parameters may be altered or tuned at runtime for dif...
Canturk Isci, Margaret Martonosi
GRID
2000
Springer
15 years 3 months ago
An Advanced User Interface Approach for Complex Parameter Study Process Specification on the Information Power Grid
The creation of parameter study suites has recently become a more challenging problem as the parameter studies have become multi-tiered and the computational environment has becom...
Maurice Yarrow, Karen M. McCann, Rupak Biswas, Rob...
ANCS
2007
ACM
15 years 3 months ago
Towards high-performance flow-level packet processing on multi-core network processors
There is a growing interest in designing high-performance network devices to perform packet processing at flow level. Applications such as stateful access control, deep inspection...
Yaxuan Qi, Bo Xu, Fei He, Baohua Yang, Jianming Yu...
ICCD
2003
IEEE
167views Hardware» more  ICCD 2003»
15 years 8 months ago
Virtual Page Tag Reduction for Low-power TLBs
We present a methodology for a power-optimized, software-controlled Translation Lookaside Buffer (TLB) organization. A highly reduced number of Virtual Page Number (VPN) bits sufï...
Peter Petrov, Alex Orailoglu
TON
2008
124views more  TON 2008»
14 years 11 months ago
Designing packet buffers for router linecards
-- Internet routers and Ethernet switches contain packet buffers to hold packets during times of congestion. Packet buffers are at the heart of every packet switch and router, whic...
Sundar Iyer, Ramana Rao Kompella, Nick McKeown