2544 search results - page 281 / 509 » Process pipeline scheduling |
148
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DATE
2006
IEEE
16 years 2 days ago
2006
IEEE
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
104
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ICMCS
2006
IEEE
16 years 2 days ago
2006
IEEE
This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves o...
161
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SIPS
2006
IEEE
16 years 1 days ago
2006
IEEE
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
166
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IEEEPACT
2005
IEEE
15 years 11 months ago
2005
IEEE
We propose a checkpoint store compression method for coarse-grain giga-scale checkpoint/restore. This mechanism can be useful for debugging, post-mortem analysis and error recover...
147
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ISCAS
2005
IEEE
15 years 11 months ago
2005
IEEE
—A high-throughput hardware architecture and FPGA implementation of the 64-bit NESSIE proposal, MISTY1 block cipher, is presented in this paper. This architecture, in contrast to...