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» Reducing the complexity of the issue logic
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ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
15 years 5 months ago
Temporal floorplanning using 3D-subTCG
Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we use a novel topo...
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-...
DIAL
2004
IEEE
156views Image Analysis» more  DIAL 2004»
15 years 3 months ago
Xed: A New Tool for eXtracting Hidden Structures from Electronic Documents
PDF became a very common format for exchanging printable documents. Further, it can be easily generated from the major documents formats, which make a huge number of PDF documents...
Karim Hadjar, Maurizio Rigamonti, Denis Lalanne, R...
IGPL
2010
97views more  IGPL 2010»
14 years 10 months ago
A symbolic/subsymbolic interface protocol for cognitive modeling
Researchers studying complex cognition have grown increasingly interested in mapping symbolic cognitive architectures onto subsymbolic brain models. Such a mapping seems essential...
Patrick Simen, Thad A. Polk
ASPDAC
2005
ACM
97views Hardware» more  ASPDAC 2005»
15 years 5 months ago
Opportunities and challenges for better than worst-case design
The progressive trend of fabrication technologies towards the nanometer regime has created a number of new physical design challenges for computer architects. Design complexity, u...
Todd M. Austin, Valeria Bertacco, David Blaauw, Tr...
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Node Mergers in the Presence of Don't Cares
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Vale...